RTU Previous Exam Papers BE EC 8th Semester VHDL Dec-2011

RTU Previous Exam Papers BE EC 8th Semester

VHDL Dec-2011

UNIT-I

1. (a) Draw the schematic for ASIC design flow and explain every step in brief.

(b) Explain the history of various hardware description language.

OR

2 (a) Explain the data flow and structural modeling scheme using suitable example.

(b) Explain the following :

(i) Entity decleration

(ii) Architecture deleration.

UNIT-II

3.(a) Explain multiplexer synthesis using Shannon’s expansion and prove Shannon’s expansion theorem.

(b) Write VHDL code 2-to-l multiplexer specifed using if-then- else statement.

OR

(a)  Write hierarchical code for 16-to-l multiplexer using structural modeling.

 

UNIT-III

3. (a) Write VHDL code for D flip-flop using a wait untill statement.

(b) Explain the comparison of level sensitive and edge trigged D-storage elements, with the help of suitable timing diagram.

OR

 (a) Write VHDL code for a four-bit up counter.

(b) Draw the schematic diagram of parallel access shift register and explain it.

 

UNIT-IV

4. (a) Draw the block diagram for MEALY-TYPE FSM and explain

it using state diagram, state table, state assigned table.

(b) Compare Mealy and Moore type FSM.

OR

(a) Write VHDL code for serial adder.

(b) Explain vending machine using timing diagram and block diagram.

 

UNIT-V

5. (a) Explain the schematic diagram of a 2m x n SRAM block and explain it.

(b) Draw the schematic diagram for the datapath circuit for the sort operation.

OR

Explain the following :

(a) Clock synchronization

(b) Design example of divider.

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