RTU Previous Exam Papers BE CSE Eight Semester
CAD for VLSI Design July 2011
1 (a) Describe two factors that make CAD tools necessary for VLSI Design. What type of specifications needed for CAD tools ?
(b) Write design flow for processing structural description of circuits on platform containing more than one FPGA. Explain each step in brief.
(a) Describe diversity of applications in the context of modern digital systems.
(b) Explain CAD flow for ASIC that take care of multiple views and design entry at different stages.
2. (a) Describe the characteristics that distinguish Hardware description language from software language.
(b) Giving example distinguish between :
(i) Concurrent and Sequential assignment.
(ii) Inertial and transport delay.
(a) List all the translations in the following using delta delay concept of VHDL.
(b) ARCHITECTURE concurrent OF timing_demo IS SIGNAL a, b, c : BIT : = ‘O’;
BEGIN a < = T; b < = NOT a; c < = NOT b; END concurrent;
Explain the following VHDL requirements :
(i) Generic Design
(ii) Timing Control
(iii) Support for Design Hierarchy
(iv) Library Support
3. (a) Explain Physical and enumeration type data in VHDL.
(b) Write a VHDL program for behavioral single bit comparator. What are the components needed for structural one bit-comparator.
(a) Explain binding alternatives in VHDL.
(b)What is test bench in VHDL ? Write a program for test bench of 4-to-l multiplexor.
UNIT – IV
4. (a) Explain the following attributes of a signal
EVENT, LAST_EVENT, LASTJVALUE, TRANSACTION
(b) Explain the concept of overloading in VHDL. Write a program that explains the concept of overloading.
(a) Distinguish between pre-defined and user-defined attributes. Giving example explain one user defined attribute.
(b) Explain the following array attributes.
RANGE, REVERSE_RANGE, LOW, RIGHT, LENGTH Write VHDL program that uses atleast two array attributes.
5 (a) What is the use of Synthetic Circuits ? How are these circuits different than Real Circuits ?
(b) Write two or more parameters used in generating Synthetic Circuits. Explain Synthetic Circuit generation process.
(a) Name three repositories that provide circuits. Write information supplied by repositories related to circuits.
(b)What is state machine synthesis ? Write a program in VHDL using state machine synthesis for a sequence detector that detects ‘1011’.