RTU Previous Exam Papers BE CS 5th Semester
Digital Logic Design Dec-2011
UNIT – I
1 (a) Why we use hardware description language and explain what is use in digital logic design?
(b) Explain different data type in HDL modeling.
1 (a) Explain different type of modeling in VHDL with example.
(b) Write a program of Ripple Carry adder in VHDL language.
UNIT – II
2 (a) Explain different kinds of subprogram with examples.
(b) Write a behavioural description of a D-flipfLop.
2. (a) What is difference of Generate and concurrent statement? Explain with suitable example.
(b) What is simulation and synthesis process in VHDL ?
UNIT – III
3 (a) Describe the steps of synchronous sequential circuit with suitable example.
(b) Explain Moore and Melay machine and describe the clock skew.
3 Discuss the concept and working principle of following : (any four)
(v) Setup time and Hold time.
4(a) What do you mean by event driven circuit ?
(b) Explain design procedure of asynchronous circuits.
(a) What is races and what is process of race free assignment ?
(b) Describe all type of Hazard in combination networks.
UNIT – V
Why we use FPGA kits and explain logic elements and programmability.
Write short notes on : (any two)
(b) Flash Memory
(c) Lookup Table Technology.