RGPV Previous year Question Paper BE(IV) SEM.Computer system and Organization- June,2007

B.E. (fourth semester) EXAMINATION, June, 2007

(Comman for CSEC &IT Engg.)

(COMPUTER SYSTEM AND ORGANIZATION)

Note:      Attempt any five questions. All question carry equal marks.

1. (a)     List at least five essential functional block that any computer should possess. Describe briefly the

              role of each block.

     (b)    Define the following:

              (i)    Instruction cycle

             (ii)    Fetch cycle

             (iii)   Decode cycle

             (iv)   Execution cycle

2. (a)     List the micro-operation  that transfer bits 1-8 of register A to bits 9-16 of register B and bits 1-8

              of register B and bits 9-16 of register A Draw a block diagram of the hardware .

    (b)    Explain various branching techniques used in micro programmed control unit .

3. (a)    Explain Booth’s algorithm  for multiplication of two fixed point number . Illustrates the same with

              a sample multiplication of two number of your choice.

   (b)     Show how computer handles floating point number and how do you perform the multiplication .

4. (a)    Draw and explain the block diagram of a DMA controller . Why read and write liens of DMA

              controller are bidirectional?

    (b)   What is an interrupt service subroutine? How can the interrupt priority be resolved ?

5. (a)    Explain  the difference between the following :

            (i) Static and dynamic RAM

            (ii) Auxiliary   memory and Associative memory

  (b)      What are the various mapping methods used with cache memory organization? Explain any one

            method in details.

6.        Differentiate between parallel processing and pipeline processing. Explain pipeline processing

           with suitable diagram.

7. (a)   Draw the block diagram for selection of next address for a control memory. Explain the function

            of each block.

    (b)    A digital computer has a memory unit of 64 k × 16 and a cache memory of 1 k words the cache

              uses direct mapping with a block size of four words. How many bits are there in the tag index.

             Block and ward fields of the address format?

8.         Write short notes on any two of the following:

           (i)  Addressing mode

           (ii)  Virtual memory

          (iii) Array processor

          (iv)  Memory management hardware

Leave a Comment