RGPV Previous Question Papers BE 4th Sem Computer System and Organization June 2006

RGPV Previous Question Papers BE 4th Semester

Computer System and Organization June 2006

(Mechanical Engg. Branch)


Note:  Attempt any five questions.

1.  (a)   What are the bottlenecks in a Von-Neumann model? Explain how the mapping from an

Instruction code to a microinstruction address can be done by means of a read only memory .

(b)   Explain the difference between hardwired control and microprogramed control. Is it possible to

have A hardwired control associate with a control memory ?

2.    (a)  What is the difference between a direct and unindirect address instruction? How many

reference to memory are needed foe each type of instruction to bring an open and into a

processor a register ? Give at least three example of each type.

(b)  Elaborate the function of the following:

(i)    Program counters

(ii)   Instruction register

(iii)  MAR

(iv)  MBR

(iv)  Accumulator

3.      (a)        Draw the timing diagram for an MVIA, 32 H instruction and explain instruction and machine


(b)            Explain why each of the following micro-operation can not be executed during a single clock





Also specify a sequence of micro-opretion that will perform the above opretion.

4.   (a)            Write an assembly language prograne to obtain the multiplection table of 12 using repetad


(b)             Explain the use of te following  instruction

(i)   DAA

(ii)   RIM

(iii) INTA

(iv) MOV   Reg,M

(v) PUSH  D

5.     (a)            How is interrupt driven I/O better than programmed I/O ?Discuss completely how the

various singles are exchanged during I/O ?

(b)           What are the basic difference between branch instructing , a call subroutine instruction

and program me interrupt ?

6.      (a)          What do you understand by the memory map ? for a 32 K memory obtain the memory

map to interface 16- bit processor .

(b)          Describe multilevel memory. What is hit ratio? Obtain the expression for average a

access time in the three level memory .

7.                      Discuss memory management in detail . Explain demand paging and swapping.

8.                    Write explanatory notes on any four of the following –

(i) Parallel processing

(ii)   Cache memory

(iii)   I/O processer

(iv)  instruction formats

(v)   DMA

(vi) DRAM

(VII)  System Bus

Leave a Comment