RGPV Previous Question Papers BE 4th Semester
Computer System and Organization Dec 2010
(Comman for CS/EC&IT, Engg.)
Note: The question paper is divided into five units. Each unit carries an internal choice. Attempt one
question from each unit. Thus attempted five questions in all. All question carries equally
marks. Assume suitable data whenever necessary.
1. (i) Explain with an example , how effective address is calculated in different types of addressing
(ii) Describe the major hardware functional unit of 8085 microprocessor eighth a neat complete
(iii) What is the difference between the two complement representation of a number and the two’s
complement of a number?
2. (i) A machine support 16 –bit instruction format. The size of address fields is 4-biy. The computer
uses expanding oppose technique. Calculate:
(a) The number of two-address instruction supported by this machine if it has n zero address
instruction and m one-address instruction.
(b) The number of zero-address instruction supported by this machine if it has n zero address
instruction and m one-address instruction.
(ii) Write program to evaluate the arithmetic statement:
P = (x-y+z)* (m*n-0) / Q+R*S
By using :
(i) Two-address instruction (ii) One-addrese instruction
(iii) Zero address instruction
3. (i) Explain booth’s multiplication algorithm .Show the step-by-step multiplication process using
booth’s algorithm to multiply the number (+15) (-13) in binary
(ii) What is the need of a control unit in a computer? What is a hardwired control unit? What are
its advantage and disadvantage? ]
4. (i) Give the flowchart for add and subtract operation of two signed 2’s compliment data. Explain
the logic of each operation.
(ii) Draw and explain the circuit diagram of 4-bit array multiplier.
(iii) With a neat block diagram, explain the working principle of micro program sequencer.
5. (I) List various commands that an interface may receive from control line of the Bus.
(ii) Explain the process of handling an interrupt that occurs during the execution of a program, with
the help of an example.
(iii) A DMA controller transfer 16-bits words to memory using cycle stealing. The words are
assembled from a device that transmits character at a rate of 2400 characters per second. The
CPU be is fetching and executing instruction at an average rate of 1 million instructions per
second. By how much the CPU be slowed down because of the DMA transfer?
6. (i) Define the following :
(a) I/O versus Memory Bus
(b) I/O interface
(c) parallel versus Serial data transfer
(ii) Explain the different techniques used for interfacing I/O device with 8085 processor. State the
merits and demerits of each.
7. (i) A digital computer has a memory unit of 64 K ×16 and a cache memory of 1K words. The cache
uses direct mapping with a block size of four words :
(a) How many bits are there in tag, index, block and word fields of the address format ?
(b) How many bits are there in each word of cache and how are they divided in to function ?
includes a valid bit.
(c) How many block does the cache accommodate?
(ii) What is associative memory? Explain the concept of match-logic for associative memories.
(iii) A computer uses RAM chips of 1024×1 capacity:
(a) How many chips are needed and how should their address lines be connected to provide a
memory capacity of 1024 bytes?
(b) How many chips are needed to provide a memory capacity of 16 K bytes? Explain in words
how the chips are to be connected to the address bus.
8. (i) A CPU has 32 bit memory address and 256 KB cache memory. The cache is organized as 4-way
set associative cache with cache block size of 16 bytes :
(a) What is the number of sets in the cache?
(b) What is the size of the tag field per cache block ?
© How many address bits are required to find the byte offset within a cache block ?
(d) What is the total amount of extra memory (in bytes) required for the tag bits ?
(ii) A virtual memory system has 6k words of address space. Page references are made by CPU in
the following sequence :
Find out the pages that are available at the end if the replacement algorithm used is
(a) LRU (b) FIFO.
Assume the page and block size of 1 K words.
9. (i) A non-pipelined system takes 100 ns to process a task. The same task can be processed in a six-
segment pipeline with a clock cycle of 20ns . Determine the speedup ratio of the pipeline for
200 tasks .What is maximum speedup that can be achieved?
(ii) Explain the various dynamics and static interconnection networks which interconnect
10. (i) Discuss all factor which affect the performance of pipelining processor based systems.
(ii) Explain the operation of a multiprocessor system with multiport memory.
(iii) Explain any one vector processing method with suitable illustration.