RGPV Exams Questions Papers IV SEM – Digital Circuit & systems – June -2002

                                                B.E. (Fourth semester) EXAMINATION, Dec. 2002

(Common for EC/EE/EX Engg.)




Note:      Solve any five questions. All question carry equal marks.

  1 (a) Design a combination circuit with 4 input line that represents BC coded and 4 output lines that

          generates the 9’s complement of the input digits.

      (b) Design a synchronous up counter with the binary sequence 0,1,3,2,6,4,5,7 by using S-R flip-flop.  

2   (a) Show how 3:8 decoders can be connected to construct a 6: 64 dector?

(b)  Convert a j-k flip-flop into an S-R flip-flop.

3. (a) Explain working of CMOS as :

(i) Inverter (ii) NAND as:

(b) Generate the digital combination circuit using MUX which detects the prime no. in 4-bit binary code.

      Take the second bit from the MSB side as the input to the MUX.

4. (a) Implement following function using minimum no. of NOR gates :

      (i) (a+b+c)  (a’+b’)  (a+c’+d)   (ii)    ab’c + ab’ + bc’

(b) Design a combination circuit that converts a 4-bit hexa-decimal code into a 7segment display.

5. (a) Use K-map to simplify the function :

          F ( A.B.C.D) = A’ (B’C + B’C’ +BCD )  + BD’  (C+A)

           D (A.B.C.D)=A’ B (C’D + C’D’) + ACD

    Where d represents don’t care terms

(b) Design a combination circuit using ROM , which multiples two 2-bit numbers.

6. (a) Implement a BCD to Excess -3 code converter by using a PLA.

(B) Find the output voltage from a 6-bit ladder that has a digital input of 101011.  Also find the full scale

       output voltage. Assume that 0=0 V and 1= +15 V.

7. (a) Explain the working of 4-bit ring counter.

(b) Explain the algorithm to shift binary no.  11001 into the serial in parallel our shift register.

8. (a) Design an even parity generator and checker for 3-bit data.

(b) Construct and explain BCD adder.


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