RGPV Exams Questions Papers IV SEM – Digital Circuit & systems – Dec -2007

                                                  B.E. (Fourth semester) EXAMINATION,NOV,DEC, 2007

(Common for EC/EE/EX Engg.)



Note:     Attempt  any five questions. All question carry equal marks.

       1  (a) (i)  By Boolean laws prove that :

                           AB+AC+BC= AB+AC .

                (II) Converter the Gary code 110101 to binary from.

                (iii) What is Minterm? Write all minterm for tree variable.

                (iv) Subtract the following number using 10’s complement method:


                 (v) Write the difference between error –detecting  code and error correcting  codes.

       (b) Find the minimal sum of products for the Boolean expression :


               Using the Quine –Mc Cluskey Method.

2.  (a) Design a half adder and half subtractor circuit. Can we use one circuit for implementing both.

      (b) Implement Y=XY+X+(Y+Z) using NAND gates only.

3.  (a) Describe the theory  behind Astable Multivibrator using (i) NOT gates and (ii) NAND gates

     (b)Draw Schmitt trigger circuit and explain with waves forms.

4. (a) Compare various logic families in terms of Basic gates , Power supply, Fan-out , power dissipation

           (?W), propagation delay and noise immunity.s

 5.(a) Draw a diagram for a 5-bitsring counter using J-K flip-flop and explain its working.

    (B) Define a code converter logic circuit by taking suitable examples.

 6. (a) Implement a full-adder circuit with multiplexers.

     (b) A combination circuit is defined by the following two function :

                     F­1(x,y) =?(0,3)

                    F2(x,y) =?(1,2,3)

   Implement the combination circuit by the decoder and external gates.

7.  (a) Discuss the performance characteristics of D to A converter.

    (b) Fig. 1 ahead shows a D to A converter along with op-amp. Fin the output of op-amp, if the input

          digital signal is 1011. Assume that binary represents 5 V.






8  Write short notes on any two of the following :

     (i) Karnaugh’s map methods

   (ii) Synchronous up-down counters

   (iii) NMOS and PMOS logic gates



Leave a Comment