NIT Jalandhar Syllabus for Low Power Design

Low Power Design Syllabus for NIT Jalandhar


 Low Power Design


Introduction: Introduction to Low-Power VLSI Design, sources of Dissipation in Digital Integrated circuit, Degree of freedom, Recurring Themes in Low power, Low Power Approaches
Device and Technology Impact on Low Power Electronics: Dynamic Dissipation in CMOS, Effect on
speed, Constrictions on Reduction, Transistor Sizing and Gate oxide Thickness, Impact of Technology Scaling


Low Power Circuit Techniques: Power consumption in circuits, Flip-Flop and Latches, Logic, High
Capacitance Nodes Low Power Clock Distribution: Power Dissipation in clock Distribution, Single Driver vs Distributed Buffer, Zero Skew vs Tolerable Skew, Chip and Package Co-Design of clock.


Logic Synthesis for low power: Power Estimation Technique, power Minimization Technique
Low power Memory Design: Sources of power dissipation in D-RAM and S-RAM, Low power DRAM
circuit, Low power SRAM circuit

Books Recommended

1. Jan M.Rabay and Massoud Pedram “Low Power Design Methodology” Kluwer Academic
Publishers 1996
2. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP, 2002
3. Rabaey, Pedram, “Low power design methodologies” Kluwer Academic, 1997
4. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design” Wiley,
5. J.M. Rabaey, A. Chandrakasan and B. Nikolic: Digital Integrated Circuits- A Design Perspective,
2nd ed., PHI, 2003

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