Mumbai University Question Papers Computer Organisation and Architecture Dec 2008
Mumbai University question papers
III Sem CSE – Examination DEC 2008
Computer Organisation and Architecture
N.B : (1) Question No.1 is compulsory.
(2) Solve any four questions out of remaining.
(3) Draw neat labelled diagram wherever necessary.
1. (a) Explain with suitable examples the difference between computer architecture and computer organization.
(b) Prove that Memory Access Time (MAT) is less than that of the memory cYcle time (MCT) with suitable example.
(c) What is bit-slice ALU? Explain in brief the structure of AMD 2901 IG and design 12 bit ALU using AMD 2901 IC.
2. (a) Explain and solve the following problem using by non-restoring division algorithm. Hence divide (10)10 with (3)1
(b) A two level memory (Ml , M2) has the access times tAl = 10- 8 sand tA2 = 10- 3 s. What must be the hit ratio H in order for the access efficiency to be atleast 65 % of it’s maximum possible value?
3. (a) A block set associative cache consists of a total of 128 cache block with two blocks/set. The main memory containing 4 K blocks with 16 words/ block. Draw a figure explaining the mapping and show the partitions of an address into TAG, SET, and WORD bit. What is cache coherency problem?
(b) Explain with state diagram,MESI (Mutual Exclusive Shared Invalid) protocol.
4. (a) Explain the general organization of CPU. State the function of following CPU registers :-
(i) MAR (Memory Address Register)
(ii) MDR (Memory Data Register)
(iii) IR (Instruction Register)
(iv) PC (Program Counter)
(v) SP (Stack :Pointer).
(b) Define “(Input/Output) I/O Module”. State the difference between programmable and non-programmable device. Explain in brief the structure of 8089 I/O processor.
5. (a) Define the term “softwired” and “hardwired”. Explain with diagram the softwired i.e. micro programmed and hardwired control unit organization.
(b) What is “Micro program”? Write a Micro program using RTL (register transfer language) notation for the following arithmetic operation :-
(i) ADDRl,R2i.e Rl~ Rl+R2
(ii) MULRl,R2 i.e Rl~ Rl*R2
6. (a) Explain. in brief about SI>ARC processor. Draw and explain. in bdef 3-bit windows architecture of SP ARC processor.
(b)’ What is the difference between pipelining & parallelism? Explain the Flynn’s Classification in detail.
7. (a) What is pipelining? Explain with suitable example the difference between serial instruction execution and pipelinedinstruction execution. Also prove that why pipelined. instruction execution is faster as compared to serial instruction execution.
(b) Explain systolic process~:>r with suitable example.