# Mumbai University Previous year question papers

Table of Contents

## III Sem CSE – Examination June 2007

## Digital Logic Design and Application

N.S (1) Question NO.1 is compulsory.

(2) Attempt any four questions out of remaining six questions.

(3) Assume suitable additional data if necessary.

1. (a) Convert (1762.46)10 to Octal, Binary and Hexadecimal.

(b) Perform the following operations without converting to any other base.

(i) (BC5)4 – (A2B)H

(ii) (63)8*

(14)8

(iii). (102.3)4 + (212.3)4

(iv) (11010)2+ (101)2′

(c) (i) Write the truth table and exitation of J-K Flip Flop.

(ii) What is a Gray Code? Give any application.

(iii) Write the Hamming Code for 1010.

2. (a) (i) Subtract using 1’s and 2’s complement method (64)10 – (31 )10′

(ii) Addition of 275 and 496 to be performed using BCD addition rules.

(iii) Implement EX-OR gate using four, two input NAND gates only.

(iv) State De-MorgonsTheorems.

(v) Simplify using Boolean Theorems and draw Logic Diagram for the following:

(i) XYZ + XYZ + XYZ + XYZ

(ii) PJ Q + R] (PQ + PR )'”

(iii) WY + WXZ + WXYZ + WXY

(iv) A + AB + (A.B) C + ABCD

3. (a) Given the logic expression-

AB + AC + C + AD + ABC + ABC

(i) Express in standard SOP form

(ii) Draw the k-map for the equation

(iii). Minimize and realise using NAND gates only.

(b) Realise the following using 16:1 MUX and 4:16 line decoder

f(A, B, C, D) = 2:m (1, 2, 4, 7, 11, 13)

4. (a) Obtain minimal expression using Quine McClusky

‘f (A, H, C, D) + 2:m (0, 1, 3, 5, 7, 10, 11, 13, 14, 15)

(b) Design a 4-bit BCD Adder using IC 7483.

,5. (a) A panel light in the control room at the launching of a satellite is to g.o ON if and only if the pressure in both fuel and oxidises tanks is equal to or abQve a required minimum and there are 10 minutes or less to lift off or if the pressure in the oxidiser tank is equal to or above a required minimum and pressure in fuel tank is below a required minimum but there are more than 10 minutes to lift oft, or if the pressure in the oxidiser tank is below a required minimum but the~e are more than 10 minutes to lift off. Design a two level combinational circuit to control panel light.

(b) Simplify f(P, Q, R, S) = nM (0, 2, 5, 7, 8, 13, 15)- d (10, 15) using K-map ‘and realise using NOR gates only.

6. (a) Design a 3 bit Up-Down Asychronous Counter with direction control Musing J-K Flip Flops.

(b) Design a Decade Synchronous Counter using J-K Flip Flops.

7. (a) Draw neat diagram of two-input TTL NAND gate and explain its operation. Also draw transfer characteristics.

(b) Write short notes on any two :-

(i) PAL and PLA

(ii) ALU

(iii). Priority Encoder.