Mumbai University Previous year question papers Microprocessor and Microcontroller Dec 2012

Mumbai University Previous year question papers

V Sem Electronics Examination Dec 2012

Microprocessor and Microcontroller

N.S.: (1) Question No.1 is compulsory.

(2) Solve any four questions out of the remaining.


1. (a) Explain internal RAM memory organization of 8051 microcontroller.

(b) Explain CPSR register of ARM? processor.

(c) Write a program for 8085 processor io convert two -digit packed BCD number  into unpacked BCD.

(d) ~xplain the SP/ EN pin of 8259 interrupt controller.


2. {a) Design and explain two wait state generator circuitary which inserts two wait states in every OPCODE FETCH machine cycle,

(b) Differentiate between I/O mapped I/O and memory mapped I/O. 10


3. (a) Design 80B5 based system with following specifications: 12

(i) CPU operating at 3 MHz

(ii) .16 KB program memory using 4 KB devices.

(iii) 4 KB data memory using 2 KB devices.

(iv~ One 8 bit input port and one 8 bit output port performing interrupt driven 1/0 and interfaced in 1/0 mapped I/O mode.Use exhaustive decoding approach.Give detailed I/O map and memory map and neat interfacing diagram.

 (b) Write 8085 based program to arrange ten data bytes in ascending order. Assume the data array begins from memory address 1000H onwards.


4. (a) Exp’lain Interruprt Enable and Interrupt Priority registers of 8051 microcontroller. 10

(b) Explain.ln’terrupt structure of 8085 processor. 10


5. (a) Interface 0808 ADC to 8051 microcontroller and write a program to take in analog input connected to input channel 0 and send the converted digital data on LED’s connected to PO.

(b) Explain Timerinternal structure in detail.



6. (a) Write 8051 based program to generate a delay of 100 m see if controller operates at 12 MHz crystal frequency. Show the delay calculations.

(b) Explain MODE 0 and MODE 1 of 8253 Timer/Counter peripheral Ie with the help of timing diagram.


7 (a) . Explain th~ instructions given below :- 10

(i) ADDS . r

(ii) ADD rD.I’D.

(iii) TST

(iv) MVN rO,

(v) ORR r~,

(b) Explaill inptll data trallsfer usinq bandslldkc sl~Jn3r-,,)! (\255 ,-‘tIll tho hero of timinn  diagram.

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