Mumbai University Previous year question papers Digital System Design I Dec 2012

Mumbai University Previous year question papers

III Sem Electronics Examination Dec 2012

Digital System Design-I

N.H. : (l) Question No.1 is compulsory.

(2) Attempt any four out of remaining six,

(3) Assume suitable data wherever necessary and state clearly.


1.(b) Obtain odd parity hamming code·for’ 1001 ‘ data. Why is hamming code ealIed error correcting code? Justify.

(c) Differentiate between combinational and sequential circuits.

(d) Constant EX-OR gate. using only NOR gates.

(e) Draw circuit of JK flip-flop using NAND gates only. Write its characteristic table and excitation table.


2. (a) Reduce following function using K-map. Get POS and SOP equations. Implement using universal gates and conclude for implementation point of view which form is more economical here ?

f= nM(l, 4, 5, 6, 7, 8, 9,14,15,22,23,25,28,29., 30, 31)

(b) Write the expression :-



(i) in standard SOP form

(ii) Write minterm list

 (Hi) Write standard POS form

(iv) Write maxterm list.


3. (a) Simplify the following using Quine-McClusky minimization technique


f(x, y., z) = Lm(l, 3, 13, 15)+ d(lO, 11)

(b) What type of static hazards may occure in a combinational logic circuit·? How it can be avoided?


4. (a) Design and explain Two’s complement Subtraetor circuit using adder Ie 7483.


(b) Implement an even parity checker for a 4 bit data, using 8 : 1 MUX and inve11crs.


6. (a) Design mod-6 ripple counter. Explain glitch problem along with waveform. 10

 (b) Design lockout free synchronous counter ·for the following state diagram using D-flip-flops.


7. (a) Draw and explain 3-bit Jhonson counter.

 (b) Write short notes on –

 (i) ALU

 (ii) Alphanumeric Codes.

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