Mumbai University Previous year question papers Digital System Design I Dec 2007

Mumbai University Previous year question papers

III Sem Electronics Examination Dec 2007

Digital System Design-I

N.S. (1) Question No. 1 is~compulsory.

(2) Solve any four out of remainingsix questions.

1. (a) ‘Draw a circuit diagram of 2 i/p TTL NAND gate. Draw its transfer characteristic and explain its operation.

(b) Find static hazards in the circuit given below and suggest modification to eliminate the hazard. 10

 

2. (a). (i) Convert to Hexadecimal number.

(245.12)10

(ii) Solve using 2’s Complement method.

(26)10- (18)10

(iii) Convert (341.13)5 to base 7 number.

(iv) Divide 11011 ~by11.

(v) Conv,ert (A2B3)H to Binary.

(b) Using K map, simplify’the’following expressions and impl~ment them using NAND gates:- 10

(i) F(A, B, C, D) =Im (1, 5, 6, 7,11,12,13) + Ld (10,15)’

(ii) F(A, B, C, D) =Im (0, 2, 5, 7, 8, 10, 13, 15).

 

3. (a) Simplify the following function using Quine McCluskey method :-

F(A. B, C, D. E) =Im (0,1,9,11,24,29,31) + Id~( 8,15,30).

(b), ,Implement the function using only one 4 : 1 mux and g~ies.

F(A. B. C, D) =In1 (0, 2, 3, 6, 8, 9, 11. 13). .

 

4. (a) Implement the following functions using active low decoder :-

(i) F(A, B) =Im (0, 1, 3) ,

 

(ii) F(A, B) = nM (0, 2. 3) (Do not convert to SOP form).

(b) Explain the features of VHDL and write a program for full adder.

 

5. (a) Implement the following functions using PLA having i/ps:’4 product terms and 2 outputs:::- 10

F1(A. B, C) =Im (3, 5, 6, 7)

F2(A, B, C) =Im (0, 2, 4, 7).

(b) Implement BCD adder using 4 bit binary adder IC 7483. Explain its operation by adding 0111 and 0110.

 

 

6. (a) braw a logic diagram of JKMS flip-flop. Write its truth tabie and derive its excitation table. Convert JKMS flip-flop to T flip-flop.

(b) Explain the working of comparator IC 7485 and implement 8,-bitcomparator using the same IC. 10

 

7. (a) Explain voltage parameters of TTL family. Also explain the current sinking and sourcing when two standard TTL g~tes are connected.

(b) Write short notes on 74180 parity generator and checker IC. 10

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