# Mumbai University Previous year question papers

Table of Contents

## III Sem CSE – Examination DEC 2012

## Digital Logic Design and Application

N.R. : (I) Question No. I is compulsory.

(2) Solve any four out otthe remaining six quest ions.

(3) Draw neat diagram wilcrcver necessary.

I. (a) Using Quine Me Cluskey method, determine the minimal SoP form for F(A, B, C, D)= ~m(4, 5, 8, 9, II, 12, 13, IS)

(b) Obtain the hamming code for Prove that hamming code is an error detecting and correcting code. _

2. (a) Implement the following using 8 : I MUX

F(A, B, C, D)= ~m(O, 1,2, 4,6, 7, 8, 10, 14, 15)

(b) D~aw a 4 bit ring counter. Draw the timi~g diagram ~d explain the working of counter. 10

3. (a) Design a sequence generator using T flip flop forthe given sequen~. Also identify .and check for lock-out condition (irany) –O~2~4~5·~O

(b) Using k-map method of minimization technique simplifY 10

F(A, B, C, D)= 1tm(1, 2, 3, 8,9, 10, 11, 14) + d(7,15)

4. (a) Explain the operation of a 4 bit universal shift register.

(b) Design a full adder circuit using half adders and some gates.

5. (a) Convert: SR to JK flip flop SR to D flip flop

(b) Compare the different logic families with respect to the following parameters Fan in, Fan out, Noise margin, speed and power dissipation.

6. (a) Convert (243’63)8 to decimal, binary (210’2)+ (312’2)4 10

(b) Draw and design a combinational circuit that multiplies two 2-bit numbers A I A2 and B I B2 to produce a 4 bit product C3 C2 CI CO.

7. Write short notes on :-

(a) De Morgans Theorem.

(b) Decade Counters

(c) Race around condition in flip Oop

(d) PLA and PAL.