# Mumbai University question papers

Table of Contents

## III Sem CSE- Examination June 2006

## Digital Logic Design and Application

Note:

(1) Q. No.1 is Compulsory.

(2) Answer any four questions from the remaining.

(3) All questions carry equal marks.

(4) Figures to the right indicate full mrks.

(5) assume suitable data if required.

1. (a) State Demorgan’s Theorems. Convert the following (761.514) 8to binary, base 4 and hexadecimal.

(b) Convert the given number (135)6 to gray code. Explain the uses of Gray Code.

“~Subtract the following using l’s complement and 2’s complement;

(62)8-(29)10

(d) Write the Hamming Code for 1010.

(e) Perform direct~ywithout converting to any other base.

(i) (F2F.7)H- (753.Al)

‘(ii) (63)8 X (21)&

(iii) (C9)~– (80)H

2. (a) Simplifythefollowln~:- – —

1. A+ 1\B+AB~+ABCD

AC[ABD]+ ABCD+ ABC

3. AB+ ABC + A (B + AB) –

(b) Given the logic Expression: A + BC + ABD + ABCD

(i) Express it in standard SOP *forml*

(ii) Draw K map and Simplify

(iii) DrawlogicDiagramusingNORgatesonly.

(iv) Draw logic Diagram using NAND gates only.

(v) Express it in standard POS form

3. Using K – Maps Simplify’ “, a. F (P,Q,R,S) =Lm (2, 3,6,7,8,9,10,11,12) +d(12) And implement using minimum number of gates.

b. Simplify F (L,M,N,O) = II M(3,4,5~6,7,10,11,15) And implement using minimum number of gates.

.4. (a) A lawn sprinkling system is controlled automatically by certain combination of The following variables:

Season (S= 1 if summer; 0 =otherwise)

Moisture content of soil (M = 1 if high; 0 if low)

Outside temperature (T= l’ ifhigh ; 0 iflow)

Outside Humidity (H = 1 ifhigh ; 0 if low )

The sprinkler is turned ON under any of the following circumstances:

(i) The moisture content is low in winter.

.(ii) The temperature is high and moisture content is low in summer.

(iii) The temperature is high and hwnidity is high in summer.

(iv) The temperature is low and moisture content is low in summer.

(v) The temperature is high and humidity is low.

Simplify and draw logic circuit diagram using universal NAND gates only.

(b) Reduce using Quine Mc Clusky method and implement using AOI gates.

F (w,x,y,z) = ITM(I,3,4,5,9,1O,11) * d ( 6,8)

5. (a) Design a mod 10 asynchronous down counter. What is glitch problem? How do. you remove the glitch?

(b) Explain in detail the “Race Around Condition” . What are the condition to occur It? How do you remove the same?

6. (a) Compare the different logic families with the following parameters;

Fan In , Fan Out, Noise Margine, Speed, Power Dissipation etc

(b) Draw neat circuit diagram of two input TIL NAND gate and explain its operation.

(c) Explain in briefTri–State Register.

7. (a) What is a PAL andPLA ?

(b) Using a ROM implement the following fW1ctions :-

f) = * :L’ *(0,1,2,5 )

f2 =*L *(1,2,3,4 )

f3 = r (0,3,5.6)

(c) E~plain in brief the concept of FPGA.