Mumbai University Pervious Year Question Papers Digital Logic Design and Application Dec 2006

Mumbai University Question Papers

 III Sem CSE – Examination DEC 2006

Digital Logic Design and Application

Note: (1) Q. No. lis Compulsory.

, (2) Answer any four questions from the remaining.

(3) Allque.stions carry equal marks.

(4) Figures to the right indicate full mrks.

(5) assume suitable data! if required.

, 1. (a) Convert (47.3)7 TO B~DI Excess- 3 I and1,GrayCode.

(b) Perform the followingoperation using 2′ s complement method

(i) (246) 7-(435 )10

(Ii) (45) 10 * (23 ) 10

@ bPerform the followingoperation with out converting into any other base. (4)

(i) (213 ) 4 * (22) 4

(ii) (ADD) H * (AD)H

(d) Explain in brief combinational PLD’S.

(e) State Distribution Laws for simplification of Boolean equation and prove it.

2. (a) Obtain HammingCode for the data (1101).Why HammingCode is called as Error Detecting Code (4)

(b ) GivenLogicEquation F= AB+ AC+ C+ AD+ ABC+ A~C

(i) Design K-Map for the given Equation. (.4)

(ii) Express in SOP Eq~ation. (4)

(iii) Minimise and Realise the above equation using NOR gates only. (4)

(iv)Realise the above equation in Standard pas and using NAND gates only. (4)

3.(a) Minimise the following equation using NOR gates only. (5)

F(W,X,Y.Z)= n M ( * d( 7,15)

(b) Provethe follwingequation using BooleanLaws. (5)

(i) (B+A ) ( C+D) (A+ C) ( B+D) =BC+AD

(II) (A.B. A) (A B B) = A8B

@ what is a carry look ahead adder. design 4 bit carry look ahead adder using gates. (5)

(d)A Car manufacturing Company wants to design a logiccct. to allow the car to start only in the following condition

(i) only when driver and front seat co- passenger are sitting with their seat belt on.

(ii) if no passenger is sitting and only the driver is sitting with the seat belt on.

4.(a) (i) Implementthe following expression using only one 8 : I Mux. and few gates. (5)

F =~m (0,1,3,4,5,7,9,10,1£,13,15)

(ii) ImplementthefollowingexpresJionusingonlyone4 : 1Mux.andfewgates. (5)

F=~m (0,1,2,3,6, 7,9,10,13;15)

(b) Using the Quine Mc Cluskey Method minimization technique simplify

F = ~m ( 1,2,6,8,10,11,14,15) + d (5,9)

5.(a) Draw J – K flip !flop usingNAND gates only and explain RACE ARROUND , CONDITION. (6)

(b )Obtain Characteristics table for S- R flip!flop , Characteristics equation, and excitation table. .

«J Explain with neat diagram interfacing ofTTL wi~hCMOS and vice versa. (8)

.6. (a) for the two functions of four variables,.1 (10)

F (W,X,Y, Z) = Lm (5,8,9,12, 13) !

F (W,X,Y,Z) = Lm (1,3,5,8,9,11)

Implement it with (i) PLA (ii) PAL ,

(b) Using Controlled Invertor Logic, design adder/subtractor cct. For 4 bits.

7. (a) Explain Two ilp TTL Nor gate and draw the cet. (10)

(b) Write short notes on (any two) : (10)

(i) universal Gates

(ii) ALU

(iii) Parity Generator

(iv. ) Self ComplementingCode.

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