JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008
( Common to Electronics & Communication Engineering, Bio-Medical
Engineering and Electronics & Telematics)
1. With neat sketches necessary, explain the oxidation process in the IC fabrication
2. (a) Draw an nMOS transistor model indicating all the components.
(b) Explain latch up problem in CMOS circuits.
3. (a) Discuss in detial the NMOS design style.
(b) Discuss CMOS design style. Compare with NMOS design style.
4. Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit.
5. (a) Explain how a Booth recoded multiplier reduces the number of adders.
(b) Draw circuit diagram of a one transistor with transistor capacitor dynamic RAM and also draw its layout.
6. (a) Draw the typical standard-cell structure showing regular-power cell and explain it.
(b) Draw and explain the pseudo-nMOS PLA schematic for full adder and what are the advantages and disadvantages of it.
7. (a) Explain how VHDL is developed and where it was used initially.
(b) What are the different design capture tools? Explain them briefly.
8. (a) Explain how function of system can be tested.
(b) Explain any one of the method of testing bridge faults.
(c) What type of faults can be reduced by improving layout design?