JNTU Previous Exam Papers B.Tech 3rd Year Linear And Digital IC Application Nov 2008

JNTU, B.Tech 3rd Year LINEAR AND DIGITAL IC APPLICATION, November 2008

( Computer Science & Engineering, Information Technology and

Computer Science & Systems Engineering)

SET-4

 

 

1. (a) Why is it necessary to use an external offset voltage compensating network

with practical OP-AMP circuits? [3]

(b) Compare and contrast an ideal OP-AMP and practical OP-AMP. [5]

(c) Explain the precautions that can be taken to minimize the effect of noise on an OP-AMP circuit. [5]

(d) Calculate the effect of variation in power supply voltages on the output offset

voltage for an inverting amplifier circuit. [3]

 

2. (a) Explain how multiplier can be used to modulate and demodulate an AM signal

[8]

(b) Discuss the differences between the differential amplifiers used in the first two stages of opamp. [8]

 

3. (a) What feedback is preferred for oscillators and why? What is the effect of negative feedback? [8]

(b) Design an OP-AMP based relaxation oscillator and derive the frequency of

oscillation. [8]

 

4. (a) Explain the operation of Monostable multivibrator using 555 timer. Derive

the expression of time delay of a Monostable multivibrator using 555 timer.

[10]

(b) Design a Monostable multivibrator using 555 timer to produce a pulse width

of 100 m sec. [6]

 

5. (a) Explain in detail the following terms with reference to PLL

i. Lock range

ii. Capture range

iii. Capture transient

iv. Pull-in-time. [8]

(b) i. Draw the internal functional diagram of NE 566 VCO and derive expres-

sion for free running frequency.

ii. From the given component values find the free running frequency Control

voltage VC = 10.9V , VCC = 12V , R1=4.7k and C1=1.1nF. [8]

 

6. (a) Explain the operation of a delay equalizer circuit with neat sketches. Derive

an expression relating input and output voltages of the equalizer. [8+2]

(b) For the all pass filter, determine the phase shift between input and output at

f=2 kHz. To obtain a positive phase shift. What modifications are necessary

in the circuit? [6]

 

7. (a) When do we prefer H.T.L. (High-Threshold Logic) gate? And explain why?

[4]

(b) Draw the Integrated circuit of H.T.L. 3-input NAND gate, and explain its

operation with the help of Truth Table. [10]

(c) Find out the average power dissipation of the gate. [2]

 

8. (a) i. Compare weighted resistor D/A converter and R-2R D/A converter.

ii. Why successive approximation D/A converter is preferable than parallel

comparator A/D converter. Explain. [8]

(b) Draw the schematic block diagram of Dual-slope A/D converter and explain

its operation. Derive expression for its output voltage Vo. [8]

 

 

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