JNTU PAPERS III B-Tech Supplimentary Examinations, Vlsi Design Aug/Sep 2008

JNTU PAPERS

JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

                                                                                                                    Vlsi Design

( Common to Electronics & Communication Engineering, Bio-Medical

Engineering and Electronics & Telematics)

SET-IV

1. With neat sketches, explain in detail, all the steps involved in electron lithography

process.

 

2. (a) Derive an equation for rds of an n channel enhancement MOSFET in linear

region.

(b) Plot the transfer characteristic of an nMOS inverter as a function of Vds.

 

3. (a) Discuss in detial the NMOS design style.

(b) Discuss CMOS design style. Compare with NMOS design style.

 

4. (a) Explain the requirement and operation of pass transistors and transmission gates.

(b) Compare pseudo-n MOS logic and clocked CMOS logic.

 

5. (a) How can the components of CMOS system design be categorized into the groups.

(b) Why is the static 6 transistor cell used for average CMOS system design?

(c) Compare the performance of CMOS Off chip and On chip memory designs.

 

6. (a) Draw a self timed dynamic PLA and what are the advantages of it compared to footed dynamic PLA.

(b) Explain the tradeoffs between using a transmission gate or a tristate buffer to implement an FPGA routing block.

 

7. (a) What are the different types of operators used in VHDL? Give some examples

using this.

(b) Compare the Circuit-level, Logic-level, switch-level and Timing simulations.

 

8. (a) Explain the gate level and function level of testing.

(b) A sequential circuit with ?n? inputs and ‘m’ storage devices. To test this circuit how many test vectors are required.

(c) What is sequential fault grading? Explain how it is analyzed.

Leave a Comment