JNTU IV B.Tech I Semester Supplimentary Examinations, February 2008

JNTU IV B.Tech I Semester Supplimentary Examinations, February 2008

VLSI SYSTEMS DESIGN

SET-II

1. Implement the following gates with CMOS Logic and explain its working

(a) 2 – Input NAND gate.

(b) 3 – Input NOR gate.

 

2. (a) Why CMOS technology is most suitable for VLSI ICs?

(b) Compare between CMOS and bipolar technologies.

 

3. Explain clearly about different parasitic capacitances of an n-MOS transistor.

 

4. Compute the high-to-low delay of a two-input static complementary NOR gate with minimum-sized transistor driving these loads.

(a) An inverter with minimum-sized pull up and pull down.

(b) An inverter whose pull up and pull down are both of size W = 10? L = 10?.

 

5. Explain the procedure to optimize power consumption of an isolated logic gate.

 

6. Draw the structure of Wallace-tree multiplier and explain its working.

 

7. Explain clearly block placement phase of the Floor planning of the chip with suitable examples.

 

8. Draw the state transition graph for the kitchen timer chip’s controller.

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