JNTU IV B.Tech I Semester Supplimentary Examinations, February 2008

JNTU IV B.Tech I Semester Supplimentary Examinations, February 2008

VLSI SYSTEMS DESIGN

SET-III

1. Implement the following gates with CMOS Logic and explain its working

(a) 2 – Input OR gate.

(b) 4 – Input NAND gate.

 

2. Name different IC fabrication technologies with suitable examples.

 

3. Design a stick diagram for CMOS logic shown below. Y = (AB + CD)1

 

4. Design a layout for CMOS 3 – input OR gate.

 

5. Explain clearly the Job of the four types of simulators that are most commonly used for combinational logic design.

 

6. Draw the structure of a carry skip adder and explain its working principle.

 

7. Explain clearly block placement phase of the Floor planning of the chip with suitable examples.

 

8. Explain clearly about technology independent logic optimization.

Leave a Comment