JNTU III B-Tech Supplimentary Examinations Vlsi Design Aug/Sep 2008

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JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

                                                                                                                 Vlsi Design

( Common to Electronics & Communication Engineering, Bio-Medical

Engineering and Electronics & Telematics)

SET-I

1. With neat sketches explain BICMOS fabrication process in an N well.

 

2. (a) With neat sketches, explain the transfer characteristic of a CMOS inverter.

(b) Derive an equation for Ids of an n-channel enhancement MOSFET operating in saturation region.

 

3. Design a stick diagram and layout for the NMOS logic shown below Y = (A + B)C.

 

4. (a) Explain clocked CMOS logic, domino logic and n-p CMOS logic.

(b) In gate logic, compare the geometry aspects between two -input NMOS NAND

and CMOS NAND gates.

 

5. (a) Draw the top level schematic and a floor plan for 16 × 16 Booth recoded multiplier and explain its operation.

(b) Explain the tradeoffs between open, closed, and twisted bit lines in a dynamic

RAM array.

 

6. (a) Draw and explain the Antifuse Structure for programming the PAL device.

(b) Explain how the I/O pad is programmed in FPGA.

 

7. (a) Write a architecture for a 4- bit Counter in both behavioral and structural styles.

(b) Explain with example how mixed mode simulator are more for CMOS circuits testing.

 

8. (a) What are the reasons of malfunctioning of chip? What are the different levels of testing?

(b) Explain how a parallel scan is used for data path test.

(c) What is mean by level sensitive of logic system?

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