JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

MICROPROCESSORS AND INTERFACING

SET-I

1. It is necessary to check weather the word stored in location 4000H:A000H is positive

number or not? Show all possible ways of testing the above condition and store 00H if the condition is satisfied in location 3000:2002. Otherwise store 0FFH.

 

2. (a) Explain in detail the coding template for 8086 MOV instruction?

(b) Write briefly about

i. PUBLIC directive

ii. EXTERN directive

 

3. (a) What is the purpose of ALE, BHE, DT/R and DEN pins of 8086? Show their timing in the system bus cycle of 8086?

(b) Why 8086 memory is mapped into 2 byte wide banks? What logic levels are found with BHE and A0 when 8086 reads a word from the address 0A0AH?

 

4. (a) What is BSR mode operation? How it is useful in controlling the interrupt initiated data transfer for mode 1 and 2?

(b) Explain the transistor buffer circuit used to drive 7-segment LEDs?

 

5. (a) With a neat sketch explain 8237 DMA controller and its operation?

(b) How do we connect RS-232C equipment

i. To data terminal type devices?

ii. To serial port of SDK ?86, RS-232C connection?

 

6. (a) Write an instruction sequence that when executed will toggle the state of the read resister bit in OCW3. Assume that the 8259 is located at memory address 00A0H.

(b) How do you set or clear the interrupt flag IF? What is its importance in the interrupt structure of 8086?

(c) How 8259 can be programmed for rotating interrupt request priorities. Ex- plain?

 

7. In an SDK-86 kit 64KB SRAM and 32KB EPROM is provided on system and provision for expansion of another 64KB SRAM is given. The on system SRAM address map is from 00000H to 0FFFFH and that of EPROM is from F8000H to FFFFFH. The expansion slot address map is from 80000H to 8FFFFH. The size of SRAM chip is 32KB. EPROM chip size is 16KB. Give the complete memory interface and also the address map for individual chips? [16]

 

8. Draw and discuss the formats and bit definitions of the following SFR’s in 8051

microcontroller?

(a) PSW

(b) IE

(c) SCON

(d) TMOD

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