JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008


(Information Technology)


1. Implement the following gates with p-MOS transistors only and explain its working

(a) 2 Input AND gate.

(b) 4 Input NOR gate.


2. An p-MOS transistor is operating in the triode region with the following parameters

?nCox = 95 ? A/V 2 W/L ( ratio) = 90 V gs = ?4V, Vtn = ?1.1V, Vds = ?2V .

Find its drain current & drain -Source resistance.


3. Explain about different spice – parameters of MOS transistor and their significance.


4. Implement 3-input NOR gate and 2 input AND gates using static complementary logic.


5. Explain clearly the Job of the four types of simulators that are most commonly used for combinational logic design.


6. Draw the circuit diagram of resistive load SRAM cell and explain its working principle.


7. Explain clearly the detailed routing phase of the floor planning of the chip with few examples by considering all constraints.


8. Draw the ASM chart for the kitchen timer controller.

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