JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008
VLSI SYSTEMS DESIGN
1. Implement the following gates with CMOS Logic and explain its working
(a) 2 Input OR gate.
(b) 4 Input NAND gate.
2. Explain working principal of n-MOS transistor with sketches of its structure.
3. Explain with neat sketches CMOS fabrication using P – well process.
4. Design a layout for CMOS 2-input NOR gate.
5. Explain with suitable example
how to design the layout of a gate to maximize performance and minimize area.
6. Draw the basic structure of serial-Parallel multiplier and explain its working principle.
7. Explain how power – down modes reduces the power consumption of the design.
8. Explain about switch – level simulation and give rules for evaluating switch – level simulation.