JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

MICROPROCESSORS AND INTERFACING

SET-II

1. The register contents of 8086 is given below.

CS=5000H, DS=8000H, SS=9000H, ES=7000H, SI=1000H, DI=2000H, BP=0008H,

SP=0002H, AX=0000H, BX=5200H, CX=8000H, DX=2800H

Calculate the effective address and physical address of the following instructions.

(a) MOV AX, [BP+BX-24D]

(b) ADD AX, ES:[SI]

(c) PUSH CX

(d) SUB AX, [DI]

(e) MOVSB

(f) CMP AX, [DI]

(g) ADD DX, [DI+8D]

(h) MUL AX, [SI+2D]

 

2. It is necessary to define a block of data in 8086 assemble language program. The length of the block is 80,000 Bytes. Give the initialization of data segment for the above data? It is necessary to exchange second element and 70000th element in the above. Give the sequence of instructions to perform the above operation?

 

3. (a) What are the different control signals necessary for I/O read and write cycles? Show how these control signals are generated in minimum and maximum modes of 8086?

(b) Why 8086 memory is mapped into 2 byte wide banks? What logic levels are found with BHE and A0 when 8086 writes a byte into the address 0F041H?

 

4. Write the necessary instruction sequence to initialize 8255 with address 0C00H to

0C03H for the following combinations.

(a) Port A as input port in mode 1 and port B as input port in mode 1 without the interrupt driven i/o.

(b) Port A in mode 2 as output port and port B as input port in mode 0 with interrupt driven i/o.

(c) Port A in mode 0, port c upper half as input ports and port B as input port in mode 1 with interrupt driven i/o.

(d) Port A as output port in mode 1 with active interrupt, port B as input port in mode 0 and port C lower half as output port in mode 0.

 

5. (a) What is the difference between 20mA current loop and RS232-C standard?

(b) Explain the necessity of RS232 to TTL interface and draw the circuit?

(c) Draw the circuit of TTL to RS232 and explain the necessity of this interface.

 

6. It is necessary to serve 18 interrupt requests using 8259’s. The address map for the 8259’s is given from 0A00H to 0A0FH. Show the complete interface with 8086 system bus? These 18 interrupts are to be requested from interrupt type 040H on words, with edge trigged mode and auto end of interrupt. Give the initialization sequence for all 8259’s.

 

7. A target system based on 8086 processor uses less amount of SRAM. The programs

are stored in EPROM that starts from 80000H ends with the address of FFFFFH. The capacity of SRAM is 16KB interfaced at address 00000H. The chip size is 8KB. The size of EPROM is 64KB. Show the complete memory interface?

 

8. (a) Enlist salient features of 8051 family of microcontrollers?

(b) Explain with waveforms different modes of counter/timer in 8051?

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