JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

VLSI SYSTEMS DESIGN

(Information Technology)

SET-I

1. Implement the following gates with p-MOS transistors only and explain its working

(a) 2 Input NAND gate.

(b) 3 Input NOR gate.

 

2. With neat sketches explain the drain characteristics of n-MOS transistor and mark different operating regions of this device.

 

3. Design a stick diagram for CMOS logic shown below.

Y = (A + B + C + D)1

 

4. Design a layout for CMOS inverter.

 

5. (a) Explain the power calculation procedure of CMOS inverter.

(b) Explain the speed – power product significance of a logic family.

 

6. Draw the structure of carry select adder and explain its working principle.

 

7. Explain how Architecture driven voltage scaling technique reduces the power consumption of the design.

 

8. Explain about different types in the register file based data-path.

 

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