JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008

ADVANCED COMPUTER ARCHITECTURE

( Common to Computer Science & Engineering, Information Technology

and Computer Science & Systems Engineering)

SET-III

1. Explain the fast computation applications in the following areas.

(a) Energy Resources exploration.

(b) Medical, Military and Basic Research.

 

2. (a) Give the different classifications of pipeline processors.

(b) Describe the typical pipeline structure of a CPU.

 

3. (a) With a neat diagram, Explain the connection mechanism of an 8*8 Bene’s Network.

(b) Describe 2*2 switching box and its four inter-connection states.

(c) Differentiate between stage control and switch control . Give their relative importance.

 

4. (a) Describe any two associative searching algorithms.

(b) Explain the architecture of STARAN associative processor.

 

5. (a) Give the architecture of K-map in Cm* architecture. With a diagram explain how an intracluster memory access is performed?

(b) What is a cluster? How communication is possible between clusters? Explain.

 

6. (a) Describe with a suitable diagram , the dynamic coherence check configuration to avoid cache coherence.

(b) What are problems that occur while multiple processor are shared?

(c) Gives the assumption usually made regarding regarding sections.

 

7. (a) Explain any two VLSI arithmetic modules for matrix computation.

(b) Explain the VLSI computing module for the inversion of a triangular matrix.

 

8. (a) What are the 3 sections which characterize the Cray ? I computer system and explain each section with diagrams.

(b) What are the functional pipeline units in Cray ? I. Explain the concept of pipeline chaining and vector loops.

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