JNTU III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008

JNTU III B.Tech II Semester Supplimentary Examinations, Aug/Sep 2008

MICROPROCESSORS AND INTERFACING

( Common to Electronics & Communication Engineering, Electronics &

Instrumentation Engineering, Bio-Medical Engineering, Electronics &

Control Engineering and Electronics & Telematics)

SET-II

1. (a) Draw the architectural diagram of 8085 and explain the function of each block in detail

(b) Discuss about Multiplexing in 8086 microprocessor

 

2. (a) Describe the following addressing modes with some examples.

i. Indexed addressing with displacement

ii. I/O port addressing

(b) Explain the meaning of the following 8086 instructions

i. mov [3845h], bx

ii. add ax, [si]

iii. mov bx, 2956h

iv. adc ax, bx

 

3. (a) Write an ALP in 8086 to find a maximum number in the array of 10 numbers

(b) Write a recursive program in 8086 ALP to find the sum of the first “n integers

 

4. (a) Explain how static RAMs are interfaced to 8086. Give necessary interface diagram assuming appropriate signals and memory size

(b) Explain the need of DMA. Discuss in detail about DMA data transfer method

 

5. (a) Explain mode 1 input operation and mode 1 output operation in 8255 with examples

(b) Give the status word of 8255 in mode 2 and explain each bit.

 

6. (a) Write an initialization sequence for an 8259 in an 8086 based system, with an even address of 0A0H that will cause

i. Request to the edge triggered mode

ii. IR0 request to an interrupt type 30

iii. SP/EN to output a disable signal to the data bus transceivers.

iv. The ISR bits to be cleared automatically at the end of second INTA pulse.

v. The IMR to be cleared.

vi. The highest priority interrupt will be IR6.

(b) What is the minimum number of bus cycles that can occur between the time an interrupt request is recognized and the first instruction in the interrupt routine is fetched.

 

7. (a) Draw the circuit of RS232 to TTL conversion and explain this interface?

(b) Draw the internal block diagram of 8251 USART and explain in detail about each block.

 

8. (a) Interface Data memory of 16K x 8 SRAM to 8051 and give memory map. The

Starting address of SRAM should be 0000H.

(b) Give the format of PCON in 8051 and give bit definitions.

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