JNTU II B.Tech I Semester Supplimentary Examinations, November 2008

JNTU II B.Tech I Semester Supplimentary Examinations, November 2008


( Common to Computer Science & Engineering, Information Technology

and Computer Science & Systems Engineering)SET-2



1. (a) Explain about sign magnitude and 2’s complement approaches for representing the fixed point numbers. Why 2’s complement is preferable.

(b) Give means to identify whether or not an overflow has occurred in 2s complement addition or subtraction operations. Take one example for each possible situation and explain. Assume 4 bit registers.

(c) Distinguish between tightly coupled microprocessors and tightly coupled Microprocessors.


2. Design register selection circuit to select one of the four 4-bit registers content on to bus. Give fuller explanation.


3. (a) What are the major design considerations in microinstruction sequencing?.

(b) Explain about microinstruction sequencing techniques, specifically variable format address microinstruction.


4. (a) What is the use of fast multiplication circuits. Write about array multipliers.

(b) Multiply 10111 with 10011 using booths algorithm.


5. (a) Explain how the Bit Cells are organized in a Memory Chip.

(b) Explain the organization of a 1K x 1 Memory with a neat sketch.


6. Explain the following:

(a) Isolated Vs Memory mapped I/O

(b) I/O Bus Vs Memory Bus

(c) I/O Interface

(d) Peripheral Devices


7. Explain the following in related with Vector Processing

(a) Super Computers

(b) Vector operations

(c) Matrix multiplication

(d) Memory interleaving


8. (a) Explain multiport memory organization with a neat sketch.

(b) Explain system bus structure for multiprocessors with a neat sketch.

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