JNTU II B.Tech I Semester Supplimentary Examinations, November 2008

JNTU II B.Tech I Semester Supplimentary Examinations, November 2008


( Common to Computer Science & Engineering, Information Technology

and Computer Science & Systems Engineering) SET-1




1. (a) Explain about various buses such as internal, external, backplane, I/O, system, address, data, synchronous and asynchronous.

(b) Explain about daisy chain based bus arbitration.


2. . Design a circuit to implement the following RTL instructions. Mention about control logic. Assume A,B are 4-bit registers using JK flip-flops.

A   A + B

B   A + B


3. (a) What are the design goals for a designer while deciding a hardwired or microprogrammed CU for a CPU.

(b) Explain nanoinstructions and nanometry. Why do we need them.


4. (a) How many bits are needed to store the result addition, subtraction, multiplication and division of two n-bit unsigned numbers. Prove.

(b) What is overflow and underflow. What is the reason?. If the computer is considered as infinite system do we still have these problems?.


5. (a) What is Redundant Array of Inexpensive Discs? What are the advantages of using this kind of systems?

(b) Explain different levels of RAID

6. (a) Explain programmed I/O in detail.

(b) Explain interrupt initiated I/O in detail.


7. (a) What is pipelining? Explain.

(b) Explain four segment pipelining.


8. (a) Explain multiport memory organization with a neat sketch.

(b) Explain system bus structure for multiprocessors with a neat sketch.


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