JNTU B.Tech II Semester Examinations, VLSI DESIGN, Apr/May 2008

JNTU B.Tech II Semester Examinations, VLSI DESIGN, Apr/May 2008

 ( Common to Electronics & Communication Engineering, Bio-Medical

Engineering and Electronics & Telematics)

Time: 3 hours Max Marks: 80

Answer any FIVE Questions

All Questions carry equal marks

SET-IV

1. Explain the following:

(a) Thermal oxidation technique

(b) Kinetics of thermal oxidation. [8+8]

 

2. (a) Explain the operation of BiCMOS inverter? Clearly specify its characteristics.

(b) Explain how the BiCMOS inverter performance can be improved. [8+8]

 

3. Explain the following

(a) Double metal MOS process rules.

(b) Design rules for P- well CMOS process. [8+8]

 

4. (a) Define and explain the following:

i. Sheet resistance concept applied to MOS transistors and inverters.

ii. Standard unit of capacitance.

(b) Explain the requirement and functioning of a delay unit. [4+4+8]

 

5. (a) Draw the schematic for tiny XOR gate and explain its operation.

(b) Draw the circuit diagram for 4-by-4 barrel shifter using complementary transmission gates and explain its shifting operation. [8+8]

 

6. (a) Explain the function of 4:1 Mux in PAL CMOS device with the help of I/O

structure.

(b) Explain how the pass transistors are used to connect wire segments for the

purpose of FPGA programming. [8+8]

 

7. (a) What are the advantages of Hardware Description Languages and give some

examples?

(b) Explain the different types of simulators used to predict and verify the performance of given circuit. [8+8]

 

8. (a) Draw the basic structure of parallel scan and explain how it reduces the long

scan chains.

(b) Draw the state diagram of TAP Controller and explain how it provides the

control signals for test data and instruction register. [8+8]

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