JNTU B-Tech II Semester Examinations, Vlsi Design,, Apr/May 2008
JNTU B.Tech II Semester Examinations,
, Apr/May 2008
( Common to Electronics & Communication Engineering, Bio-Medical
Engineering and Electronics & Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. (a) What is Moore’s law? Explain its relevance with respect to evolution of IC
(b) What is the size of silicon wafer used for manufacturing state-of-the art VLSI ICs?
(c) What is the minimum feature size of current commercial VLSI devices?[8+4+4]
2. Compare the relative merits of three different forms of pull up for an inverter
circuits. What is the best choice for realization in
(a) nMOS technology
(b) CMOS technology. 
3. Draw the stick diagram and a translated mask layout for nMOS inverter circuit. 
4. Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit. 
5. (a) Compare the different types of CMOS subsystem Multipliers.
(b) Design a schematic for an 8-word × 2-bit NAND ROM that serves a lookup table to implement a full adder. [8+8]
6. (a) Explain the methods of programming of PAL CMOS device.
(b) Draw and explain the architecture of an FPGA . [8+8]
7. (a) What are the different data types available in VHDL and how they are indicated?
(b) Write a VHDL program for a 4-bit Counter with Asynchronous reset. [8+8]
8. (a) Draw the basic structure of parallel scan and explain how it reduces the long
(b) Draw the state diagram of TAP Controller and explain how it provides the control signals for test data and instruction register. [8+8]