GTU previous years question papers -BE- Sem-III -Computer Organization and Architecture -December/January 2009-10

GTU previous years question papers

GUJARAT TECHNOLOGICAL UNIVERSITY

B.E. Sem-III(Computer Engineering)

Examination December/January 2009-10

Subject code: 13    

Subject Name: Computer Organization & Architecture

Total Marks: 70

Instructions:

1.      Attempt all questions.

2.       Make suitable assumptions wherever necessary.

3.       Figures to the right indicate full marks.

Q.1 (a) Define the following terms.

(i)                 Effective address

(ii)               Immediate instruction

(iii)             Register transfer language

(iv)              Sequencer

(v)                Computer organization

(vi)              Pseudo instruction

(vii)            Data Dependency

(b) Answer the following briefly

(i)     Explain selective set, selective complement and selective clear

(ii)   Show the block diagram of the hardware that implements  the following register transfer statement .

T2: R2 – R1 , R1 – R2

(iii)   Explain one, two and three address instruction.

Q.2 (a)(i) A digital computer has a common bus system for 16 registers of 32 bits    each.

(i)   How many selection input are there in each multiplexer?

(ii)   What size of multiplexers are needed?

(iii) How many multiplexers are there in a bus?

(ii) Explain the following instructions

1)                    CLA

2)                    ISZ

3)                    INP

(b) Explain 4 bit incrementer with a necessary diagram

OR

(b) Explain Instruction cycle.

Q.3 (a)(i) Write a note on subroutines.

(ii) Explain Direct and Indirect Addressing                                                                        

(b) (i) Write an assembly level program for the following pseudocode.

SUM = 0

SUM = SUM + A + B DIF = DIF – C SUM = SUM + DIF

(ii) Differentiate SIMD and MIMD.

OR

Q.3 (i) Show the contents of the registers E, A, Q, SC during the process of   multiplication of two binary numbers 11111(multiplicand) 10101 (multiplier). The signs are not included.

(b) Draw the space time diagram for six segment pipeline showing the time    it takes to process 8 tasks.

 TOC \o
"1-5" \h \z (ii) Write a note on memory interleaving.

Q.4 Explain the characteristics of RISC and CISC.

(b) Convert the following into reverse polish notation.

1)      A+B * [C*D+E*(F+G)]

2)      A*[B+C*(D+E)] / [F+G*(H+I)]

(ii) Explain various types of interrupts

OR

Q.5 Explain overlapped windows register.

(b) Explain the following terms

1)     PSW

2)      Delayed load

3)      Pipeline conflict

Explain Stack and evaluate the following expression using stack   (3+4)* [ 10(2+6)+8]

Q.5   TOC \o
"1-5" \h \z Explain the first pass of an assembler with a flowchart

(b) Explain four types of instruction formats

OR

Explain booth algorithm for multiplication with a flowchart

(b) Write a note on different addressing modes                                                         

 

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