GTU Last Year question papers Digital Logic Design

GTU Last Year question papers


B.E. Sem-III Remedial Examination May 2011

Subject code: 130701

Subject Name: Digital Logic Design



1. Attempt all questions.

2. Make suitable assumptions wherever necessary.

3. Figures to the right indicate full marks.

Q.1 Answer the following

(i) Draw symbol and construct the truth table for three input Ex-OR gate.

(ii) What is the principle of Duality Theorem?

(iii) Explain briefly: standard SOP and POS forms.

(iv) What are Minterms and Maxterms?

(v) Define: Noise margin , Propagation delay

(vi) Give comparison between combinational and Sequential logic circuits

(vii) What is race-around condition in JK flip-flop?

Q.2 (a) (i) Explain NAND and NOR as an universal gates

(ii) Convert decimal 225.225 to binary ,octal and hexadecimal

(b) (i) Implement Boolean expression for Ex-OR gate using NAND gates only

(ii) convert decimal 8620 into BCD , excess-3 code and Gray code.


(b) (i) Simplify the following Boolean function using K-map

F( w,x,y,z) = Σ( 1 , 3 , 7 , 11 , 15 ) (04)

with don’t care conditions d( w,x,y,z ) = Σ( 0, 2 ,5 )

(ii) Draw logic diagram , graphical symbol , and Characteristic table for clocked D flip-flop (03)

Q.3 (a) Design a combinational circuit whose input is four bit binary number and

output is the 2’s complement of the input binary number.


(b) Design a full-adder with two half-adders and an OR gate


Q.3 (a) Design a BCD to decimal decoder

(b) What is multiplexer? Implement the following function with a multiplexer:

F(A,B,C,D) = Σ(0 , 1 , 3 , 4 , 8 , 9 ,15 )

Q.4 (a) Write short note on : Read Only Memory (ROM)

(b) A combinational circuit is defined by functions:

F1(A,B,C) = Σ( 3 , 5 , 6, 7 )

F2(A,B,C) = Σ( 0 , 2 , 4, 7 )

Implement the circuit with PLA having three inputs ,four product term andtwo outputs



Q.4 (a) Give classification of counters and explain asynchronous  4-bit binary ripple counter

(b) Explain briefly:

(i) logic and shift micro-operations

(ii) fixed-point binary data and floating-point data

Q.5 (a) Draw block diagram of a 4-bit arithmetic logic unit. Design an adder/subtractor circuit with one selection variable S and two inputs A and B .when S = 0 circuit performs A+B, when S = 1 circuit performs A – B by taking the 2’s complement of B

(b) Draw and explain block diagram of microprograme control.


Q.5 (a) Simplify the following Boolean function using tabulation Method and

draw logic diagram using NOR gates only F(w,x,y,z ) = Σ( 0 ,1 , 2 , 8 ,10 ,11,14,15 )

(b) Explain working of master-slave JK flip-flop with necessary logic diagram , state equation and state diagram


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