Digital Signal Processing Syllabus for JNTU Kakinada

Digital Signal Processing Syllabus for JNTU Kakinada

 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY
KAKINADA
III Year B.Tech EEE II-Sem T P C
4+1* 0 4
DIGITAL SIGNAL PROCESSING
UNIT I
INTRODUCTION: Introduction to Digital Signal Processing: Discrete time signals & sequences, linear shift
invariant systems, stability, and causality. Linear constant coefficient difference equations. Frequency
domain representation of discrete time signals and systems.
UNIT II
DISCRETE FOURIER SERIES: Properties of discrete Fourier series, DFS representation of periodic
sequences, Discrete Fourier transforms: Properties of DFT, linear convolution of sequences using DFT,
Computation of DFT. Relation between Z-transform and DFS
UNIT III
FAST FOURIER TRANSFORMS: Fast Fourier transforms (FFT) – Radix-2 decimation in time and
decimation in frequency FFT Algorithms, Inverse FFT, and FFT for composite N
UNIT IV
REALIZATION OF DIGITAL FILTERS: Review of Z-transforms, Applications of Z – transforms, solution of
difference equations of digital filters, Block diagram representation of linear constant-coefficient difference
equations, Basic structures of IIR systems, Transposed forms, Basic structures of FIR systems, System
function,
UNIT V
IIR DIGITAL FILTERS: Analog filter approximations – Butter worth and Chebyshev, Design of IIR Digital
filters from analog filters, Design Examples: Analog-Digital transformations
UNIT VI
FIR DIGITAL FILTERS : Characteristics of FIR Digital Filters, frequency response. Design of FIR Digital
Filters using Window Techniques, Frequency Sampling technique, Comparison of IIR & FIR filters.
UNIT VII
MULTIRATE DIGITAL SIGNAL PROCESSING: Decimation, interpolation, sampling rate conversion,
Implementation of sampling rate conversion.
UNIT VIII
INTRODUCTION TO DSP PROCESSORS: Introduction to programmable DSPs: Multiplier and Multiplier
Accumulator (MAC), Modified Bus Structures and Memory Access schemes in DSPs Multiple access
memory, multiport memory, VLSI Architecture, Pipelining, Special addressing modes, On-Chip
Peripherals.
Architecture of TMS 320C5X- Introduction, Bus Structure, Central Arithmetic Logic Unit, Auxiliary
Registrar, Index Registrar, Auxiliary Registger Compare Register, Block Move Address Register, Parallel
Logic Unit, Memory mapped registers, program controller, Some flags in the status registers, On- chip
registers, On-chip peripherals
TEXT BOOKS:
1. Digital Signal Processing, Principles, Algorithms, and Applications: John G. Proakis, Dimitris G.
Manolakis,
Pearson Education / PHI, 2007.
2. Discrete Time Signal Processing – A.V.Oppenheim and R.W. Schaffer, PHI
3. Digital Signal Processors – Architecture, Programming and Applications,, B.Venkataramani, M.
Bhaskar, TATA McGraw Hill, 2002
Reference Books:
1. Digital Signal Processing: Andreas Antoniou, TATA McGraw Hill , 2006
2. Digital Signal Processing: MH Hayes, Schaum’s Outlines, TATA Mc-Graw Hill, 2007.
3. DSP Primer – C. Britton Rorabaugh, Tata McGraw Hill, 2005.
4. Fundamentals of Digital Signal Processing using Matlab – Robert J. Schilling, Sandra L. Harris,
Thomson, 2007.
5. Digital Signal Processing – Alan V. Oppenheim, Ronald W. Schafer, PHI Ed., 2006

Leave a Comment