CSVTU BE VIII Semester EEE VLSI Design Syllabus

CSVTU BE VIII Semester EEE VLSI Design Syllabus

Chhattisgarh Swami Vivekanand Technical University, Bhilai (C.G.)

Semester: 8th Branch: Electrical & Electronics Engg.

Subject: VLSI Design

Total Theory Periods: 40 Total Tut Periods: 12

 Total Marks in End Semester Exam: 80

 Minimum number of Class tests to be conducted: 2

 UNIT – I

Introduction to Integrated Circuits:

SSI, MSI and LSI. VLSI Design flow, Design hierarchy concept of regularity, Modularity and Locality, VLSI design styles with FPGA and CPLD.

UNIT – II

Design Aspects:

Standard cell based design, Basic steps of fabrication process of PMOS, CMOS and Bi-CMOS, layout design rules, CMOS lay out design rules, Lay out of CMOS inverter, NAND Gate, NOR Gate, Full Adder, Calculation of resistance and capacitance.

UNIT – III

Lay Out Design:

Lay out design of RAM, ROM, PLA Decoder, MUX, 4-bit Adder, Comparator, Combinational and Sequential Logic.

UNIT – IV

Combinational Logic Design:

Introduction to VHDL and Verilog, Introduction to CAD Tools, Power dissipation in Lgic gates entity, Signal Architecture, Configuration and Definition, Operators, Data Types, Generic, Generate loops, Data flow, Structural and behavioral programming, process, Procedure, Component in VHDL and Verilog, Libraries,

Case Statement..

UNIT – V

Sequential Logic Design:

Sequential design by VHDL and Verilog FSM, Bus structure in VHDL, Test bench Synthesis, Operator overloading, Blocks, Delays, Verification’s..

Recommended books :

1. Modern VLSI Design by Wolf, Pearson Education Pub.

2. VHDL Programming by Perry, TMH Pub.

Reference Books:

1. CMOS VLSI Design: A Circuits and Systems Perspective by Weste, Pearson Ecuation Pub.

2. Verilog HDL by Palntikar, Pearson Education Pub.

3. Basic VLSI Design by Pucknell & Esharghian, 3

rd

Ed., PHI Pub.

4. Modern VLSI Design – System-on-chip Design, Wolf, PHI pub.

5. Fundamentals of Digital Logic with VERILOG Design, Brown, TMH Pub.

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