CSVTU BE VI Sem EEE Computer Organization & Architecture Syllabus

CSVTU BE VI Sem EEE Computer Organization & Architecture Syllabus


Semester : VI Branch: EEE

Subject: Computer Organization & Architecture

Total Theory Periods: 40 Total Tutorial Periods: Nil

Total Marks in End Semester Examination: 80

Minimum number of Class tests to be conducted: Two

Unit I

Unit II

Unit III

Unit IV

Unit V

Central Processor organization: Bus organized computer, Memory address structure, Memory data

register, program counter, Accumulator, Instruction register, Program counter, Accumulator, Instruction

register, Instruction field, Micro operations, Register transfer languages, Instruction field, Decoding and

execution, Instruction formats and addressing modes.

Control unit organization: Instruction sequencing, Instruction interpretation, Hardwired control, Microprogrammed

control organization, Control memory, Address sequencing, Micro-instruction, Formats, Microprogram

sequence, Microprogramming.

Arithmetic processor design: Addition and subtractions algorithm, Multiplication algorithm, Division

algorithm Processor configuration, Design of control unit and floating point arithmetic.

Input Output organization: Programmed I/O., I/O, addressing, I/O instruction, Synchronization, I/O

interfacing, Interrupt mechanism, DMA, I/O processors and data communication, RISC, CISC, Loosely

Coupled & Tights Coupled system.

Memory organization and multiprocessing: Basic concepts and terminology, Memory hierarchy,

Semiconductor memories (RAM, ROM), Multiple module, Memories and interleaving (Virtual memory,

Cache memory, Associative memory), Memory management hardware requirements, RISC & CISE


1. Computer System Architecture by M. Morris Mano, PHI

2. Computer Organization Architecture by J.P. Hayes, PHI

Digital Computer Logic Design By M. Morris Mano, PHI

Structured Computer Organization by Andrew S. Tanenbaum PHI

Computer Organisation and Design, Pal-Chauduri, PHI

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