CSVTU BE IV Semester EEE Digital Electronic Circuits Syllabus

CSVTU BE IV Semester EEE Digital Electronic Circuits Syllabus

CHHATTISGARH SWAMI VIVEKANAND TECHNICAL UNIVERSITY BHILAI (C.G.)

Semester :IV Branch: Electrical & Electrionics Engg.

Subject:Digital Electronic Circuits

UNIT – I

CODES:

Binary codes:

Introduction & usefulness, Weighted & Non-weighted codes, Sequential codes, self complementing codes, Cyclic codes, 8-4-2-1 BCD code, Excess-3 code, Gray code: Binary to Gray and Gray to binary code conversion, Error detecting code, Error correcting code, 7-bit Hamming code, ASCII code, EBCDIC code.

Realization of Boolean Expressions :

Reduction of Boolean expressions using laws, theorems and axioms of Boolean Algebra, Boolean expressions and logic diagram, Converting AND/OR/Invert logic to NAND/NOR

logic, SOP and POS Forms and their Realization.

UNIT –II

MINIMIZATION TECHNIQUES:

Expansion of a Boolean expression to SOP form, Expansion of a

Boolean expression to POS form, Two, Three & Four variable K-Map: Mapping and minimization of SOP

and POS expressions. Completely and Incompletely Specified Functions – Concept of Don’t Care Terms;

Quine – Mc Clusky Method.

UNIT III

COMBINATIONAL CIRCUITS:

Adder & Subtractor:

Half adder, Full adder, half subtractor, Full

subtractor, Parallel Binary adder, Look Ahead carry adder, Serial adder, BCD adder. Code converter, Parity

bit generator/Checker, Comparator.

Decoder

: 3-line to 8-line decoder, 8-4-2-1 BCD to Decimal decoder,

BCD to Seven segment decoder.

Encoder: Octal to binary and Decimal to BCD encoder. Multiplexer

: 2-input

multiplexer, 4-input multiplexer, 16-input multiplexer

Demultiplexer:

1-line to 4-line & 1-line to 8-line

demultiplexer, Multiplexer as Universal Logic Function Generator, Programmed Array Logic (PAL).

UNIT – IV

SEQUENTIAL CIRCUITS:

Flip-Flops & Timing Circuit

: S-R Latch; Gated S-R Latch; D Latch; J-K flip-

Flop; T Flip-Flip: Edge Triggered S-R, D, J-K and T Flips-Flops; Master – Slave Flip-Flops; Direct Preset and

Clear Inputs.

Shift Registers:

PIPO, SIPO, PISO, SISO, Bi-Directional Shift Registers; Universal Shift

register.

Counter:

Asynchronous Counter: Ripple Counters; Design of asynchronous counters, Effects of

propagation delay in Ripple counters, Synchronous Counters: 4-bit synchronous up counter, 4-bit

synchronous down counter, Design of synchronous counters, Ring counter, Jhonson counter, Pulse train

generators using counter, Design of Sequence Generators; Digital Clock using Counters.

UNIT – V

DIGITAL LOGIC FAMILIES: Introduction; Simple Diode Gating and Transistor Inverter; Basic Concepts of

RTL and DTL;

TTL

: Open collector gates, TTL subfamilies, IIL, ECL; MOS Logic: CMOS Logic, Dynamic

MOS Logic, Interfacing: TTL to ECL, ECL to TTL, TTL to CMOS, CMOS to TTL, Comparison among

various logic families, Manufacturer’s specification.

Text Book:

1. Fundamentals of Digital Circuits: A. Anand Kumar, PHI

2. Digital Integrated Electronics: H. Taub and D. Schilling: TMH

Reference Books:

1. Digital Fundamentals: Floyd & Jain: Pearson Education

2. Digital Electronics: A.P. Malvino: TMH.

3. Digital Circuits & Logic Design – LEE, PH

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