CHARUSAT EC Digital Electronics and Logic Design Syllabus

CHARUSAT EC Digital Electronics and Logic Design Syllabus

CHAROTAR UNIVERSITY OF SCIENCE & TECHNOLOGY
FACULTY OF TECHNOLOGY & ENGINEERING
V. T. PATEL DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
B. TECH. (ELECTRONICS & COMMUNICATION)
2ND YEAR SEMESTER: III
EC 201: DIGITAL ELECTRONICS & LOGIC DESIGN
______________________________________________________________________

Credit Hours:
Teaching Scheme
Theory
Practical
Total
Credit
Hours/week
4
2
6
5
Marks
100
50
150
A. Objective of the Course:
This course will introduce the students about fundamentals of digital electronics including number systems, Boolean algebra and logic gates, combinational logic, designing of combinational and sequential circuits.
B. Outline of the Course:
Sr.
No.
Title of the Unit
Minimum Number of Hours
1.
Number Systems
04
2.
Boolean Algebra and Logic Gates
06
3.
Simplification of Boolean Functions
08
4.
Combinational Logic
09
5.
Combinational Logic With MSI AND LSI
09
6.
Sequential Logic
12
7.
Registers, Counters and the Memory Unit
12
Total Hours (Theory):60
Total Hours (Lab): 30
Total Hours:90
© CHARUSAT 2012 Page 18 of 154
C. Detailed Syllabus:
1.
Number Systems 4 Hrs
8%
1.1
Digital Computer And Digital Systems, Binary Number, Number Base
Conversion Octal And Hexadecimal Number
1 Hr
1.2
Complements, Binary Codes
2 Hr
1.3
Binary Storage And Register, Binary Logic, Integrated Circuit
1 Hr
2.
Boolean Algebra And Logic Gates 6 Hrs
10%
2.1
Basic Definition, Axiomatic Definition of Boolean Algebra, Minterm And Maxterms
2 Hrs
2.2
Basic Theorem And Properties of Boolean Algebra
3 Hrs
2.3
Logic Operations, Digital Logic Gates, IC Digital Logic Families
1 Hr
3.
Simplification of Boolean Functions 8 Hrs
12%
3.1
Two-Three Variable K-Map, Four- Five Variable K-Map
2 Hr
3.2
Product of Sum Simplification, NAND or NOR Implementation
2 Hrs
3.3
Don’t Care Condition
2 Hr
3.4
Tabulation Method
2 Hrs
4.
Combinational Logic 9 Hrs
15%
4.1
Introduction, Design Procedure, Hazards
3 Hrs
4.2
Adder, Sub tractor
3 Hrs
4.3
Code Conversion, Universal Gate, Exclusive OR & Equivalence Functions
3 Hrs
5.
Combinational Logic With MSI And LSI 9 Hrs
15%
5.1
Introduction, Binary Parallel Adder
2 Hr
5.2
Decimal Adder, Magnitude Comparator
2 Hrs
5.3
Decoder, Multiplexer
2 Hrs
5.4
ROM, PLA, PAL
3 Hrs
6.
Sequential Logic 12 Hrs
20%
6.1
Introduction, RS,JK,D,T Flip-Flops, Triggering of Flip-Flops
3Hrs
6.2
Flip-Flop Excitation Tables, Analysis of Clocked Sequential Circuits
3 Hrs
6.3
State Reduction And Assignment Design Procedure
3 Hrs
© CHARUSAT 2012 Page 19 of 154
6.4
Design of Counters, Design With State Equations
3 Hrs
7.
Registers, Counters And The Memory Unit 12 Hrs
20%
7.1
Introduction, Registers, Shift Registers
4 Hrs
7.2
Ripple Counters, Synchronous Counters
4 Hrs
7.3
Timing Sequences, Memory Unit, Johnson Counter
4 Hrs
D. Instructional Method and Pedagogy:
 Multimedia Projector
 OHP
 Chapter wise Assignments
 Quiz
 Audio Visual Presentations
 Chalk + Board
 White Board
 Online Demo
E. Student Learning Outcomes:
 To Design combinational circuits on bread board
 To design different flip-flops
 To simulate on VHDL software
F. Recommended Study Material:
 Reference Books:
1. Digital Logic and Computer Design By M Morris Mano, PHI- Publication 2002
2. Digital Principles and Application by Malvino & Leach, THI-1999
3. Digital System Design Using VHDL , Charles H. Roth, Thomson,2002
 Web Materials/ Reading Material:
http://zebu.uoregon.edu/~rayfrey/432/DigitalNotes.pdf
http://smendes.com/el10b/gates1.gif
1) Lab Manuals
2) Hand Outs
3) Assignments
4) Question Bank

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