# Anna University Model Question Paper BE V sem E&I MICROPROCESSORS AND MICROCONTROLLERS

MODEL QUESTION PAPER

B.E. ELECTRICAL AND ELECTRONICS ENGINEERING

FIFTH SEMESTER

EI 331 – MICROPROCESSORS AND MICROCONTROLLERS

Time: 3 Hours                                                                                          Max. Marks: 100

PART – A (10 x 2 = 20 marks)

1. Specify the single instruction, which clears the most significant bit of B register (of 8051), without affecting the remaining bits.

1. Give the alternate functions for the port pins:

P 3.3 and P 3.6

1. What is the purpose for which the signal ALE is available in 8085 and 8086?

1. What is the purpose for which the signal ‘Ready’ is available in 8085 and 8086?

1. What happens in 8086 processor, when

i)                    overflow of sum occurs during addition of signed numbers.

ii)                  overflow of quotient occurs during division operation.

1. What is the operation performed by the instruction CBW (of 8086). Give an example for its use.

1. Formulate the control word for setting bit Pc4 of 8255 high using BSR modes.

1. What is the purpose for which the ‘auxiliary carry’ flag is available in Intel processors?

1. What is the necessity for providing 4 banks of general purpose registers R0 to R7 in 8051? How can you switch over to bank1 from bank0?

1. Name the following interfacing ICs:

8253, 8237, 8259 and 8279.

PART – B (5 x 16 = 80 Marks)

1. With a neat sketch, discuss the architecture of Intel 8085, bringing out its salient features.

12.a)    Discuss the operation performed by the following 8085 instructions. Specify the addressing modes used by these instructions. Discuss how these instructions affect/are affected by the various flags. Also state the machine cycles and no. of T-states taken by these instructions:

ADC B, CMP M, DAA and LDA 1234H

# OR

12.b)    Discuss the operation performed by the following 8086 instructions. Also formulate the binary codes (OPCODE) for these instructions, using the templates given below:

ii)      XCHG CH, ES: [BX]

Templates:

 0 0 0 0   0 0 d w
 Mod  reg    r/m
 Disp – 10w
 Disp – high
 0 0 0      0                    w
 Mod  reg    r/m
 XCHG          reg/mem
 with reg:
 0 0      reg code            0

(if any)

Segment        over ride      prefix:

13.a)    With a help of a functional block diagram, explain the features available in the micro controller Intel 8051. What are the extra features available in Intel 8052?

# OR

13.b)    Draw the timing diagram explaining the execution of the 8085 instruction:

SHLD 1234H. The opcode for SHLD instruction is 22H.

14.a)    Write assembly language programs, in 8085 and 8086, for adding consecutive bytes available form location INPUTNO onwards. The 16-bit result must be stored at location RESULT.

### OR

14.b)i)  ‘8086 employs a pipe lined architecture’ – Elaborate.

ii)  Discuss the segment memory concept used in 8086.

15.a)    The figure shows interfacing a Thumb-Wheel Switch and two numbers of seven-segment LEDs to 8085 through a 8255-PPI:

Identify the address (es) for the control register and ports. Frame the control word required. Write a program which displays the ‘square’ of the number input from Thumb-wheel Switch (TWS) at the two 7-segment displays after a time delay of one minute. Also discuss how would you implement this application on 8051.

### OR

15.b)    Discuss the features available in 8251 – USART, along with a functional block diagram, mode/control word format and an example application.

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