Anna University Linear Integrated Circuits Exam Paper

Anna University Linear Integrated Circuits Exam Paper

IV Semester ET & T


Time : Three hours                                                                        Maximum : 100 marks

Answer ALL questions.

PART A — (10 ´ 2 = 20 marks)

1. With reference to an OP AMP, define supply voltage rejection ratio.

2. In response to a square wave input, the output of an OP AMP changed from
–3V to +3V over a time interval of 0.25                         s. Determine the slew rate of the

3. State the important features of an instrumentation amplifier.

4. Using an OP AMP, draw the circuit diagram of a phase shift oscillator.

5. What is a two quadrant multiplier?

6. With reference to a PLL, define ‘Pull in Time’.

7. The basic step of a 9 bit DAC is 10–3 mV. If 000000000 represents 0V, what is the output for an input of 101101111?

8. Why does the dual slope ADC provide excellent noise rejection of AC signals whose periods are integral multiples of the integration time?

9. Using a 555, draw the circuit diagram of an astable multivibrator.

10. State the limitations of linear voltage regulators.


PART B — (5 ´ 16 = 80 marks)

11. Draw the circuit diagram of a symmetrical emitter coupled difference amplifier and derive an expression for the difference mode gain Ad and the common mode gain Ac.

12. (a)     Design a fourth order Butterworth low pass filter having a upper cutoff frequency of 1 KHz.


             (b)     Design a square wave oscillator for f0 = 1 KHz using 741 OP AMP and a DC supply voltage of 12 V.

13. (a)     Draw the basic block diagram of a 566 VCO and derive an expression for the VCO output frequency.


             (b)     Using neat sketches, explain how a PLL can be used as (i) a frequency translator and (ii) a AM demodulation.

14. (a)     Draw and explain the functional diagram of the successive approximation A/D converter.


             (b)     A dual slope ADC uses a 16 bit counter and a 4 MHZ clock rate. The maximum input voltage is +10 V. The maximum integrator output voltage should be –8V when the counter has cycled through zncounts. The capacitor used in the integrator is 0.1 . Find the value of the resistor R of the integrator. If the analog signal is +4.129 V, find the corresponding binary number.

15. (a)     (i)      Draw a neat sketch showing the noise voltage and noise current characteristics of the OP–27/37 op. amp.

                       (ii)    Show that the figures of merit in op amp noise performance are the white noise floors  and  and the corner frequencies  and .


             (b)     Write short notes on :

                       (i)      Power op amps.

                       (ii)    Fiber optic ICs.

                       (iii)   Optocouplers.


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