JNTU III B.Tech Supplimentary Examinations, Aug/Sep 2008


(Information Technology)


1. Implement the following logic functions using CMOS logic

(a) Y = {AB + (C + D)}1

(b) Y = {A(B + C) + D}1


2. Explain working principal of P-MOS transistor with sketches of its structure.


3. Explain with neat sketches CMOS fabrication using n – well process.


4. Compute the high-to-low delay of a two-input static complementary NOR gate with minimum-sized transistor driving these loads.

(a) An inverter with minimum-sized pull up and pull down.

(b) An inverter whose pull up and pull down are both of size W = 10? L = 10?.


5. Explain with suitable example the details of single – Row layout design method.


6. Draw the structure of carry select adder and explain its working principle.


7. Explain clearly the global routing phase of the floor planning of the chip with few examples by considering all constraints.


8. Write a register-transfer description of one four-digit timer.

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