Anna University Computer Architecture I Question Paper


             Anna University Computer Architecture I Question Paper

FOURTH SEMESTER-COMPUTER ARCHITECTURE — I

COMPUTER SCIENCE & ENGINEERING

Time : Three hours                                                                        Maximum : 100 marks

Answer ALL questions.

PART A — (10 ´ 2 = 20 marks)

1.Discuss briefly about the basic functional units of a computer.

2.What must an instruction set specify?

3.Draw the block diagram of a 2′s complement Adder/Subtractor.

4.With the help of a common layout, explain briefly the representation of a floating–point number.

5.The address of a memory location to be accessed is in register R1 and the memory data are to be loaded into register R2. Specify the sequence of operations involved.

6.Briefly discuss the basic organization of a microprogrammed control unit.

7.What are the different types of ROMs? Discuss.

8.Explain the concept of virtual memory.

9.Summarize the sequence of events in handling an interrupt request from a single device. Assume that the interrupts are enabled.

10.What is a synchronous bus? Draw the timing diagram for an input transfer on this bus.

PART B — (5 ´ 16 = 80 marks)

11.Explain the various addressing modes available for the basic computer system.

  1.                                                                                                                                             (a)(i) Multiply the following pair of signed 2′s complement numbers using the Booth algorithm :

       A = 010111 (Multiplicand)

       B = 110110 (Multiplier)

  (ii)Discuss anyone technique for speeding up the multiplication operation.

Or

(b)With the help of a logic diagram, explain the operation of a floating point adder subtractor unit.                                    (16)

(a)Explain with a block diagram, the organization of a hardwired–control

  1.                    unit.                                                                                                                        (16)

Or

(b)(i)Give the structure of an m–stage pipeline.                                     (4)

 (ii)Explain with a neat sketch, a 2–stage pipelined microprogram  control unit.
(12

(a)Explain the following mapping procedures for the organization of Cache–memory :

 (i) Associative mapping                                                                           (8)

 (ii) Direct mapping.                                                                                   (8)

Or

  (b) (i)Explain with a suitable example, the relocation of memory blocks using compaction method.                                                                  (8)

(ii) Discuss any two useful page replacement policies.                        (8)

(a)Explain the following data transfer schemes with neat diagrams :

 (i)Interrupt driven data transfer.                                                         (8)

 (ii) DMA data transfer.                                                               (8)

Or

 (b)Explain with a neat diagram, the principle of operation of a Black–and–White Video monitor.                   (16)

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